The present invention relates to a method for testing a controller using random pattern generation techniques. More particularly, the present invention relates to a method for testing an integrated drive electronics (IDE) controller model by use of a computer simulation environment.
An IDE controller is a device which controls the flow of data traffic between the main memory of a computer system and one or more peripheral devices, coupled to the computer system via the IDE controller. One such peripheral device, for example, is an IDE disk drive. When employed in a personal computer system, an IDE controller must be proven to operate with many different types of IDE devices, such as hard disk drives, CD ROMs, etc. A typical IDE controller has many programmed modes of operation which must be tested to effectively verify that the IDE controller functions for its intended purpose. Therefore, it is necessary to test combinations of many parameters in order to ensure compatibility with all such disk drives. Also, variations in speed and features are numerous in modern IDE disk drive models making the design of an IDE controller that properly functions with these operational variations even more difficult. An apparatus for testing IDE controllers, commonly known as a xe2x80x9ctest bench,xe2x80x9d may test, for example, combinations of the following parameters: 1. Drive Transfer Mode (single-word DMA, multi-word DMA, synchronous DMA, programmed IO); 2. Drive Under Test (master or slave drive); 3. Timing Parameters (command pulse width, relaxation time, set-up time, pause time); 4. Transfer size (16 or 32 bit-wide transfers, number of sections); 5. Prefetch or Read Ahead Mode (enabled, disabled); and 6. Bus Mastering constraints (PRD, memory starting address, transfer byte count, single/multi-PRD transfers).
Previous methods of testing IDE controller designs required an on-line human operator to choose a particular combination of test constraints for each individual test case. After a particular combination of constraints was tested, the operator would then formulate another combination of test constraints and run that test, and so on. This xe2x80x9chuman centeredxe2x80x9d approach to IDE controller testing is cumbersome and often results in inadequate testing of an IDE controller due to human error or a lack of human resources. Therefore, a more efficient and comprehensive method of testing IDE controller models is needed.
The present invention addresses the above and other needs by providing a method of testing IDE controller models, which are simulated in a computer system, in a comprehensive fashion with minimal human resources. Through software, a xe2x80x9ctest benchxe2x80x9d is set up which includes simulations of an IDE controller model (HDL description or gate level rendition), a bus functional model (BFM) used to generate input/output traffic over a host interface, and models of IDE compatible devices. This test bench is then compiled into a logic simulation environment and operated.
In one embodiment of the invention, a method of testing an IDE controller includes: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.
In another embodiment, the method described above further includes the acts of: generating random test constraints, programming the IDE controller with the random test constraints, and randomly generating the data patterns. One method of implementing the acts of generating the random test constaints and data patterns includes the acts of: generating a random binary number having a specified number of bits, wherein the random test constraints and the random data patterns are each represented by at least one bit of the random binary number.
In a further embodiment, a method of testing an IDE controller includes the acts of: providing an IDE controller model having primary and secondary channels and a host interface; testing the primary channel by transmitting a first set of test data across the primary channel; testing the secondary channel by transmitting a second set of test data across the secondary channel, wherein the secondary channel is tested concurrently with the primary channel; and arbitrating access to the host interface between the primary and secondary channels. As used herein, the term xe2x80x9cconcurrentlyxe2x80x9d refers to the condition in which two or more steps, processes or procedures are occurring at the same time. The two or more steps, processes or procedures may occur dependently or independently of one another.
The embodiments of the invention disclosed herein overcome the above-referenced long-standing problems in the IDE controller industry by providing a method which automatically and comprehensively tests IDE controller models which are simulated in a computer simulation environment. By generating random test constraints in accordance with specified criteria, the invention significantly reduces the amount of time a human operator needs to spend in testing each IDE controller model. Additionally, the concurrent testing of two or more channels of the IDE controller model further reduces the testing time of an IDE controller model when compared to testing each channel of the IDE controller model separately.